1. Field of the Invention
This invention relates to computer systems, and more particularly, to address decode circuitry.
2. Description of the Related Art
To access a certain address in a memory array, a set of address signal is applied to address decoding logic associated with the memory array. The address decoder logic may then decode the address signal and allow access to a location in the memory array that corresponds to an address indicated by the state of the various address signals.
For some types of memory arrays, addressing the array is not such a straightforward process as described above. For example, register files in some x86 processors, still bound by the legacy of the x87 instruction set, include a special zone. If an address is received by the address decoder indicates a location within the special zone, the actual address to be accessed may be different from the received address. In other words, the address may be rotated by a specified amount. The number of locations within the special zone that the address is rotated (i.e. shifted) is indicated by a set of rotate signals.
FIG. 1 illustrates one embodiment of such a memory system. The memory array includes 64 separate locations, and thus requires 6 address bits. These address bits are conveyed to a rotation logic unit. Locations 24-31 of the array comprise a special zone, and thus any address received by the rotation logic unit that falls within this special zone may be rotated. In addition to receiving the address, the rotation logic may receive signals indicating a rotation value, i.e. a number of locations in which the address is to be shifted. It should be noted that the addresses are rotated in a circular fashion, and thus if a rotation value causes an address to be rotated beyond one extreme of the special zone (e.g. location 31) then the next location to which the address is shifted is the other extreme (location 24). For example, if the address received is location 30, and the address is to be rotated right by 3 locations, the address is actually shifted to location 25 (30 to 31, 31 to 24, and 24 to 25).
After the rotation logic has determined if an address is to be shifted and by how many locations if so, it may output a modified address. If after checking the address and determining that it falls outside of the special zone, the rotation logic may output the originally received address. Address output by the rotation logic, whether modified or not, is then received by the address decode logic. The address decode logic then decodes the address and accesses the memory at the appropriate location.
The operation shown herein is performed in a serial manner, and thus is subject to a delay. This delay may adversely impact the speed at which the memory system operates. In certain embodiments (e.g., wherein the memory array is a register file in a processor), the performance impact may be significant, and may thus cause a bottleneck.